Phase noise or phase jitter of carrier signals is a major limiting factor in many Radio Frequency (RF) communications systems as it can significantly affect the performance of systems. While in an ideal world it is possible to look at perfect carrier signals with no phase noise, this is not the case in real communication systems. Instead, all signals have some phase noise or phase jitter in them. For radio receivers, phase noise on local oscillators within the system can affect specifications such as reciprocal mixing and the noise floor. For transmitters it can affect the wideband noise levels that are transmitted. Additionally it can affect the bit error rate on systems using phase modulation as the phase jitter may just cause individual bits of data represented by the phase at the time to be misread.
System aspects require the use of low cost crystals with strict control. Traditional phase noise control is based on Analog Phase Lock Loops (APLLs). The emerging Digital Phase Lock Loop (DPLL) is a digital realization of the APLL, preserving functionality and performance. However phase lock loop is inherently suboptimal due to causality, delay in the loop and stability considerations. One benefit of DPLL is the availability of digital phase error metrics (EM).
Transmit phase noise is traditionally handled by PLL. Receivers provide additional phase noise cancelation schemes, commonly based on pilots or decoded data. These schemes combat thermal noise and multipath channel and heavily depend on signal framing and appropriate training.
Thus, there is a need for improved concepts of phase noise or phase error mitigation.